In a switched capacitor network, one or more capacitors are switched between different signals. In the context of an analog-to-digital converter (ADC), a set of capacitors may be charged by an input signal source during a sample phase, then switched to being connected to a reference voltage source during a hold (amplify) phase. When the capacitors are switched back to the input signal source during the next sample phase, residual charge stored on the capacitors can become superimposed onto the value of the input signal source in this sample phase. Part of this “kick-back” can be sampled by the input network at the end of this sampling phase, which can cause distortion of the sampled signal, memory effects and performance degradation. The kick-back is non-linear in that the amount of charge injected back into the ADC is not a linear function of the value of the input. Thus, it is not possible to correct for the kick-back using only the input value, e.g., by scaling the input value.
The problem of non-linear kick-back will now be explained in connection with FIGS. 1 to 3, which illustrate portions of a conventional ADC, in which an input voltage is compared to a set of reference voltages to generate a digital output. FIG. 1 shows a block diagram of a conventional multi-stage pipelined ADC. Three stages 100/110/120 are connected in succession so that the output of one stage may serve as the input of the next stage. For illustration purposes, only the first two stages and the final (Nth) stage are shown. However, any number of stages can be connected in this fashion. The first stage 100 is connected to an analog input voltage Vin and includes an ADC 10 (also known as a “flash”) and a multiplying digital-to-analog converter (MDAC) 50. The MDAC 50 includes a digital-to-analog converter (DAC) 20 and an amplifier 30. Vin is input to the ADC 10 to generate a digital input to the DAC 20, which in turn converts the digital output of the ADC 10 back into an analog signal. The analog output of the DAC 20 is then subtracted from Vin and the result input to the amplifier 30 to generate an analog output voltage Vo as input to the next stage, i.e., stage 110. The stages 100/110/120 may include similar components, with the analog output of one stage going into the input of the next stage in order to perform an analog-to-digital conversion of Vin. However, the final stage, i.e., stage 120, may not include a DAC or amplifier since the final output of the ADC is a digital signal that can be generated, for example, directly from the output of the ADC 10.
FIG. 2 shows a block diagram of the ADC 10. Vin is compared in parallel, by a set of comparators 12, to a respective set of reference voltages having values ranging between 7/16*VFS and − 7/16*VFS, where VFS is the full-scale voltage of the stage 100. The output of each comparator 12 forms an individual bit of a digital output signal FL of the ADC 10, for a total of eight bits FL0 to FL7, which collectively form a thermometric code. However, the number of bits output may vary in other embodiments. In one example, when Vin is at a value V1, FL is 0 0 0 0 1 1 1 1, with the left-most bit being the most significant, i.e., corresponding to FL7 in FIG. 2. Continuing the example, when Vin is at a value V2, FL is 0 0 1 1 1 1 1 1.
FIG. 3 shows a schematic diagram of the stage 100. Although shown as a single line in FIG. 1, Vin may actually be input to the ADC 10 as a differential input in the form of a pair of complementary voltages Vin+/Vin− that have equal magnitude, but opposite polarity. Vin+ and Vin− are switchably connected to a respective set of eight capacitors 8C in parallel (the actual number of such capacitors may vary across different implementations, and even between different stages). The capacitors 8C are also switchably connected to Vref+ and Vref−, which are positive and negative reference voltages of equal magnitude and opposite polarity, around a reference common-mode level. The stage 100 operates as follows: During the sample phase, Vin+ and Vin− are connected to first terminals of all eight of their respective capacitors 8C, the amplifier 30 is reset and second terminals of the capacitors 8C are shorted together to a common mode voltage VCM. During a hold phase, Vin+ and Vin− are disconnected from the capacitors 8C, the amplifier is enabled and, as explained below, the capacitors 8C are selectively connected to Vref+ and Vref− based on the sampled values of Vin+ and Vin−.
The DAC 20 may convert the digital output of the ADC 10 into an analog signal by selectively connecting the capacitors 8C in response to the ADC 10 output. At the same time, the connection of the capacitors 8C may also be selected to reflect the subtraction of the DAC output from Vin, shown symbolically in FIG. 1 as a summation node 17. In one example, when Vin has a value of V1 (i.e., Vin+ minus Vin− equals V1 for differential implementation), four capacitors in each set of eight capacitors 8C may be connected to Vref+ and four capacitors connected to Vref−. On the other hand, when Vin has a value of V2, six capacitors in the set 8C associated with Vin+ may be connected to Vref+ and two capacitors connected to Vref−. Correspondingly, when Vin equals V2, six capacitors in the set 8C associated with Vin− may be connected to Vref− and two capacitors connected to Vref+. From this example, it can be seen that when Vin equals V1, zero charge is dumped back into the input when the capacitors 8C are reconnected to Vin+ and Vin− during the next sample phase, since the contributions of the capacitors cancel out. However, when Vin equals V2, a net charge of 6C*Vref−2C*Vref, i.e., 4C*Vref, is dumped back into the input (i.e., kick-back).
Depending on the sampling frequency and input source characteristics, the input source cannot always absorb the kick-back charge completely. If the disturbance is not fully absorbed by the time the next sample is taken, it distorts Vin by transferring residual charge back into the ADC. As previously explained in connection with the operation of the DAC 20, the amount of this residual charge depends on the ADC 10 output, i.e., the quantized value of the previous input by ADC 10.
One known method of reducing kick-back is to short the capacitors 8C together using a switch, in order to discharge as much charge as possible before reconnecting the capacitors back to the input. A disadvantage to this method is that it reduces the time available for connecting to Vin, so that it becomes more difficult to acquire the input. Additionally, the timing of the control signal required to control the switch that shorts the sample capacitors (capacitors 8C) before connecting them back to the input is difficult to control accurately.
Another known method of reducing kick-back is to use a separate set of capacitances for sampling the input from those used for the DAC, e.g., a set of dedicated DAC capacitors would be provided in addition to the sample capacitors (capacitors 8C). However, this degrades the feedback factor of the MDAC amplifier and causes signal-to-noise ratio (SNR) degradation.